1. Field of the Invention
The invention relates to operational amplifiers, particularly to an operational amplifier supporting a HALF AVDD structure and implemented using traditional twin-well CMOS transistors.
2. Description of the Related Art
If continuously applied with a DC voltage, the liquid crystal material is damaged. To prevent the damage to the liquid crystal material, the polarity of each data signal applied to the liquid crystal material is periodically inverted (so-called AC driving), as well know in the art. With respect to traditional liquid crystal display (LCD) driving integrated circuits (IC) operating at a positive voltage system, only two operating voltages AVDD (13.5 V or 16V) and VSS are provided (hereinafter called “AVDD structure”). Based on the AVDD structure, after a channel voltage is pulled down from AVDD to VSS, charges are normally wasted. Accordingly, the ratio of power consumption of a traditional LCD panel to total power consumption is up to 70%; besides, as the sizes of the LCD panels are getting larger, it further causes overheating of the panels.
An effective solution has been proposed to deal with the above-mentioned problem. In addition to the two operating voltages AVDD and VSS, a third operating voltage HALF AVDD (hereinafter called “HALF AVDD structure”) is provided to the LCD driving IC. The feature of the HALF AVDD structure is that charges are collected while positive channels discharge to the operating voltage HALF AVDD and then the collected charges are provided for negative channels to charge via the operating voltage HALF AVDD. Accordingly, the HALF AVDD structure saves power consumption and prevents overheating of LCD panels. FIG. 1 is a schematic diagram showing two conventional operational amplifiers supporting the HALF AVDD structure and four switches located at two neighboring channels Y(n) and Y(n+1) in a source driver (not shown). Referring to FIG. 1, the operational amplifier 110, supporting the HALF AVDD structure and located at the channel Y(n), operates between AVDD and HALF AVDD while the operational amplifier 120, supporting the HALF AVDD structure and located at the channel Y(n+1), operates between HALF AVDD and VSS. The voltages of positive analog image signals A+ generated by the operational amplifier 110 range from AVDD to HALF AVDD while the voltages of negative analog image signals A− generated by the operational amplifier 110 range from HALF AVDD to VSS. By controlling four switches SW1˜SW4, a positive analog image signal A+ and a negative analog image signal A− are alternately output from the channels Y(n) and Y(n+1) to the panel for every predetermined period of time.
However, according to the prior arts, MOS transistors fabricated using triple-well CMOS process are prerequisite for the operational amplifiers 110 and 120 able to support the HALF AVDD structure. Take a NMOS transistor for example; an additional process of a deep n-well is required to isolate a p-well and a p-substrate according to the triple-well scheme. The triple-well CMOS process is a high-cost technology and not popular yet in Taiwan. However, it is sure that the cost of the triple-well CMOS process must be higher than that of the twin-well CMOS process.